1. Field of the Invention
This invention relates to dynamic random access memory (DRAM) technology, and more particularly, to a delay circuit provided to each memory cell in a DRAM device for use to assist the measurement of the charge/discharge period of each DRAM cell more precisely. Moreover, the invention relates to a delay chain circuit which is formed by chaining a plurality of such delay circuits together to allow the charge/discharge period measurement to be performed in a collective manner on all the DRAM cells in the delay chain circuit, which can be then used to determine the charge/discharge period of each DRAM cell.
2. Description of Related Art
As integrated circuit technology advances, the fabrication of DRAMs has now entered into the deep-submicrometer and nanometer levels of integration and the DRAM operation speed is now at sub-nano-second levels. At such fast operation speeds, however, the parasite resistance in a DRAM device would become nonnegligible, which would then adversely affect the performance of the DRAM device.
Fundamentally, each DRAM cell includes a capacitor, called data-storage capacitor, to store binary data in such a manner that when the data-storage capacitor is charged, it represents the storage of a first binary value, for example 1; and when discharged, it represents the storage of a second binary value, for example 0. In DRAMs that use a deep-trench capacitor, the buried strap would be very high in electrical resistance, thus reducing the operating current in the access operation to the DRAM, causing the data stored on the capacitor to be easily lost when the switching speed on the word lines is very fast. The access speed to the DRAM is therefore limited by this factor. Accordingly, in the design of DRAMs, it is required to measure the DRAM charge/discharge period precisely.
FIG. 1 is a schematic diagram showing the equivalent circuit of a conventional DRAM cell As shown, the conventional DRAM cell includes a MOS transistor TMC, a buried-strap resistor RBS, a deep-trench resistor RDT, a data-storage capacitor CDT, and a poly-contact resistor RCB. The MOS transistor TMC has a gate connected to a word line to receive a gate voltage VGin, a first source/drain end connected via the poly-contact resistor RCB to receive a system voltage VCC, and a second source/drain end connected via the buried-strap resistor RBS and the deep-trench resistor RDT to the data-storage capacitor CDT. The other end of the data-storage capacitor CDT is connected to a buried-plate voltage VBP. The system voltage VCC is used to represent a high-voltage logic state for the DRAM, while the buried-plate voltage VBP is used to represent a low-voltage logic state for the DRAM.
One drawback to the foregoing DRAM cell structure, however, is that it would be impossible to measure the voltage variation at the data-storage capacitor CDT from the storage node in the DRAM cell. This is because that the connection pads in the DRAM has a very high capacitance that would significantly affect the access speed to the DRAM cell; and in addition, the DRAM charge/discharge period is too short to allow precise measurement.